Field of the Invention
The present invention relates generally to the field of computer systems, and in particular to methods and mechanisms for processing memory transactions.
Description of the Related Art
To prioritize the movement of memory requests through a system on chip (SoC) fabric, a quality-of-service (QoS) mechanism may be implemented such that an agent generating a memory request may also provide information representing the QoS level associated with that request. In a typical scenario, arbiters and queues in the path of a memory request or transaction containing QoS information should be capable of processing that information—or at least of forwarding the information to a subsequent circuit which is then capable of processing it.
A SoC may include a coherence point to act as a gateway between the coherent and non-coherent domains of the SoC. The coherence point may include a queue for storing in-flight transactions. Utilizing a QoS-aware arbiter to decide which transactions to read out of the queue may be expensive in terms of size and power. Therefore, to reduce the size and power consumption of the SoC, a non-QoS-aware arbiter may be used in the coherence point. However, this may lead to performance issues if reordering of transactions in the coherence point causes a loss of the already performed QoS-based arbitration already.